The Effect of High Temperature Annealing on Fluorine Distribution Profile and Electro-Physical Properties of Thin Gate Oxide Fluorinated by Silicon Dioxide RIE in CF4 Plasma

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DOI:

https://doi.org/10.26636/jtit.2010.1.1059

Keywords:

capacitance-voltage characteristics, current-voltage characteristics, fluorine plasma, high temperature annealing process, radio frequency reactive ion etching

Abstract

This study describes the effects of high temperature annealing performed on structures fluorinated during initial silicon dioxide reactive ion etching (RIE) process in CF4 plasma prior to the plasma enhanced chemical vapour deposition (PECVD) of the final oxide. The obtained results show that fluorine incorporated at the PECVD oxide/Si interface during RIE is very stable even at high temperatures. Application of fluorination and high temperature annealing during oxide layer fabrication significantly improved the properties of the interface (Ditmb decreased), as well as those of the bulk of the oxide layer (Qeff decreased). The integrity of the oxide (higher Vbd) and its uniformity (Vbd distribution) are also improved.

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References

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Submitted

2023-06-27

Published

2010-03-30

Issue

No. 1 (2010)

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ARTICLES FROM THIS ISSUE

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How to Cite

[1]
M. Kalisz, G. Głuszko, and R. B. Beck, “The Effect of High Temperature Annealing on Fluorine Distribution Profile and Electro-Physical Properties of Thin Gate Oxide Fluorinated by Silicon Dioxide RIE in CF4 Plasma”, JTIT, vol. 39, no. 1, pp. 25–28, Mar. 2010, doi: 10.26636/jtit.2010.1.1059.

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