Semiconductor cleaning technology for next generation material systems
DOI:
https://doi.org/10.26636/jtit.2007.2.807Keywords:
III-V compounds, FinFET, IC manufacturing, MEMS, MOS gate stack, semiconductor cleaningAbstract
This paper gives a brief overview of the challenges wafer cleaning technology is facing in the light of advanced silicon technology moving in the direction of non-planar device structures and the need for modified cleans for semiconductors other than silicon. In the former case, the key issue is related to cleaning and conditioning of vertical surfaces in next generation CMOS gate structure as well as deep 3D geometries in MEMS devices. In the latter, an accelerated pace at which semiconductors other than silicon are being introduced into the mainstream manufacturing calls for the development of material specific wafer cleaning technologies. Examples of the problems related to each challenge are considered.
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