Challenges for 10 nm MOSFET process integration
DOI:
https://doi.org/10.26636/jtit.2007.2.805Keywords:
sstrained silicon, silicon germanium, silicon-oninsulator (SOI), high-k dielectrics, hafnium oxide, nano-wire, low-frequency noise, mobility, metal gateAbstract
An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.
Downloads
References
[1] International Technology Roadmap for Semiconductors (ITRS), 2005, http://www.itrs.net/Common/2005ITRS/Home2005.htm
View in Google Scholar
[2] A. Dixit et al., "Analysis of the parasitic S/D resistance in multiple-gate FETs", IEEE Trans. Electron Dev., vol. 52, pp. 1132-1140, 2005.
View in Google Scholar
[3] J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime", in Tech. Dig. IEDM, San Francisco, USA, pp. 57-60, 2000.
View in Google Scholar
[4] D. Hisamoto et al., "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm", IEEE Trans. Electron Dev., vol. 47, pp. 2320-2325, 2000.
View in Google Scholar
[5] J.-W. Yang and J. G. Fossum, "On the feasibility of nanoscale triple-gate CMOS transistors", IEEE Trans. Electron Dev., vol. 52, pp. 1159-1164, 2005.
View in Google Scholar
[6] L. Mathew et al., "Inverted T channel FET (ITFET) - fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45 nm and beyond CMOS", in Tech. Dig. IEDM, Washington, USA, 2005, pp. 731-734.
View in Google Scholar
[7] S. D. Suk et al., "High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): fabrication on bulk Si wafer, characteristics, and reliability", in Tech. Dig. IEDM, Washington, USA, 2005, pp. 735-738.
View in Google Scholar
[8] J. Hallstedt et al., "A robust spacer gate process for deca-nanometer high-frequency MOSFETs", Microelectron. Eng., vol. 83, pp. 434-439, 2006.
View in Google Scholar
[9] Y.-K. Choi, T.-J. King, and C. Hu, "A spacer patterning technology for nanoscale CMOS", IEEE Trans. Electron Dev., vol. 49, pp. 436-441, 2002.
View in Google Scholar
[10] Y.-K. Choi, T.-J. King, and C. Hu, "Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era", Solid-State Electron., vol. 46, pp. 1595-1601, 2002.
View in Google Scholar
[11] S. Gannavaram, N. Pesovic, and C. Ozturk, "Low temperature (800°C) recessed junction selective silicon-germanium source/drain technology for sub-70 nm CMOS", in Tech. Dig. IEDM, San Francisco, USA, 2000, pp. 437-440.
View in Google Scholar
[12] C. Isheden et al., "MOSFETs with recessed SiGe source/drain junctions formed by selective etching and growth", Electrochem. Solid State Lett., vol. 7, pp. G53-G55, 2004.
View in Google Scholar
[13] M. A. Quevedo-Lopez et al., "High performance gate first HfSiON dielectric satisfying 45 nm node requirements", in Tech. Dig. IEDM, Washington, USA, 2005, pp. 237-240.
View in Google Scholar
[14] M. von Haartman et al., "Low-frequency noise and Coulomb scattering in Si0.8Ge0.2 surface channel pMOSFETs with ALD Al2O3 gate dielectrics", Solid-State Electron., vol. 49, pp. 907-914, 2005.
View in Google Scholar
[15] H. Iwai et al., "Advanced gate dielectric materials for sub-100 nm CMOS", in Tech. Dig. IEDM, San Francisco, USA, 2002, pp. 625-628.
View in Google Scholar
[16] A. C. Jones et al., "Recent developments in the MOCVD and ALD of rare earth oxides and silicates", Mater. Sci. Eng. B (Solid-State Mater. Adv. Technol.), vol. 118, pp. 97-104, 2005.
View in Google Scholar
[17] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, "The effect of high-k gate dielectrics on deep submicrometer CMOS device and circuit performance", IEEE Trans. Electron Dev., vol. 49, pp. 826-831, 2002.
View in Google Scholar
[18] D. Wu et al., "A novel strained Si0.7Ge0.3 surface-channel pMOSFET with an ALD TiN/Al2O3 HfAlOx/Al2O3 gate stack", IEEE Electron Dev. Lett., vol. 24, pp. 171-173, 2003.
View in Google Scholar
[19] L.-A. Ragnarsson et al., "High performing 8 Å EOT HfO2/TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown (SPER) junctions", in Tech. Dig. VLSI Symp., Kyoto, Japan, 2005, pp. 234-235.
View in Google Scholar
[20] H.-C. Wen, K. Choi, P. Majhi, H. Alshareef, C. Huffman, and B. H. Lee, "A systematic study of the influence of nitrogen in tuning the effective work function of nitrided metal gates", in IEEE Int. Symp. VLSI Technol., Hsinchu, Taiwan, 2005, pp. 105-106.
View in Google Scholar
[21] H. Wakabayashi, Y. Saito, K. Takeuchi, T. Mogami, and T. Kunio, "A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film", IEEE Trans. Electron Dev., vol. 48, pp. 2363-2369, 2001.
View in Google Scholar
[22] Y. H. Kim et al., "Systematic study of work function engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks", in Tech. Dig. IEDM, Washington, USA, 2005, pp. 657-660.
View in Google Scholar
[23] A. Lauwers et al., "CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON", in Tech. Dig. IEDM, Washington, USA, 2005, pp. 661-664.
View in Google Scholar
[24] M. Leskelä and M. Ritala, "Atomic layer deposition (ALD): from precursors to thin film structures", Thin Solid Films, vol. 409, pp. 138-146, 2002.
View in Google Scholar
[25] C. Claeys, E. Simoen, A. Mercha, L. Pantisano, and E. Young, "Low frequency noise performance of HfO2 based gate stacks", J. Electrochem. Soc., vol. 152, pp. F115-F123, 2005.
View in Google Scholar
[26] D. Wu et al., "Influence of surface treatment prior to ALD high-k dielectrics on the performance of SiGe surface-channel pMOSFETs", IEEE Electron Dev. Lett., vol. 25, pp. 289-291, 2004.
View in Google Scholar
[27] M. von Haartman et al., "Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics", Solid-State Electron., vol. 48, pp. 2271-2275, 2004.
View in Google Scholar
[28] M. von Haartman, B. G. Malm, and M. Ostling, "Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-k gate dielectrics and TiN gate", IEEE Trans. Electron Dev., vol. 53, pp. 836-843, 2006.
View in Google Scholar
[29] M. von Haartman et al., "Influence of gate width on 50 nm gate length Si0.7Ge0.3 channel PMOSFETs", in Proc. 33rd Eur. Solid-State Dev. Res. Conf. ESSDERC'03, Estoril, Portugal, 2003, pp. 529-532.
View in Google Scholar
[30] S. E. Thompson et al., "A logic nanotechnology featuring strained-silicon", IEEE Electron Dev. Lett., vol. 25, pp. 191-193, 2004.
View in Google Scholar
[31] E. Kasper and K. Lyutovich, "Strain adjustment with thin virtual substrates", Solid-State Electron., vol. 48, pp. 1257-1263, 2004.
View in Google Scholar
[32] P.-E. Hellström et al., "Strained-Si NMOSFETs on thin 200 nm virtual substrates", in Solid State Dev. Res. Symp., Bethesda, USA, 2005.
View in Google Scholar
[33] J. Seger, P. E. Hellstrom, J. Lu, B. G. Malm, M. von Haartman, M. Östling, and S. L. Zhang, "Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator", Appl. Phys. Lett., vol. 86, pp. 253507-1, 2005.
View in Google Scholar
[34] J. Seger, "Interaction of Ni with SiGe for electrical contacts in CMOS technology", Ph.D. thesis, KTH - Royal Institute of Technology, Sweden, 2005.
View in Google Scholar
Downloads
Submitted
Published
Issue
Section
License
Copyright (c) 2023 Journal of Telecommunications and Information Technology
This work is licensed under a Creative Commons Attribution 4.0 International License.
