CONTI, Vincenzo; VITABILE, Salvatore. Design Exploration of AES Accelerators on FPGAs and GPUs. Journal of Telecommunications and Information Technology, Warsaw, Poland, v. 67, n. 1, p. 28–38, 2017. DOI: 10.26636/jtit.2017.1.647. Disponível em: https://www.jtit.pl/jtit/article/view/647. Acesso em: 10 jul. 2026.